Low temperature performance of self-aligned ”Etched Polysilicon” emitter pseudo-heterojunction bipolar transistors

In this paper we present an investigation of the static performance over the 300K-80K temperature range of pseudo-heterojunction bipolar transistors using an advanced single-polysilicon CMOS compatible self-aligned structure and epitaxial growth for the base and the low doped emitter spacer. These devices exhibit ideal collector currents and non-ideal base currents. By analysing the base leakage current, we have been able to identify the main critical fabrication steps. The bandgap narrowing in the base has been deduced from the temperature dependence of the collector current and the effect of a parasitic boron spike in the base doping profile on the low temperature performance of the transistor has been studied.